This invention relates to line receivers and, more particularly, to differential ECL tri-state detection receivers.
Differential drivers and receivers are utilized in numerous applications. Typically the outputs of a differential driver are coupled to the inputs of a differential receiver via a bus. A typical differential receiver consists of a pair of differentially coupled transistors such that their emitters are tied together and the base of one transistor is coupled to a non-inverting input of the differential receiver, while the base of the other transistor is coupled to the inverting input of the differential receiver. Further, the collector of one transistor is coupled to a voltage potential by a first resistor, while the collector of the other transistor is coupled to a voltage potential by a second resistor. When a differential driver goes into a tri-state mode, both the inverting and non-inverting outputs are typically pulled down to a predetermined level, thereby typically producing a logic low at both the inverting and non-inverting inputs of the differential receiver. However, a logic low occurring at both inputs of the differential receiver typically causes the differential receiver to oscillate and forces the outputs of the differential receiver to unknown logic states.
One attempt that prior art has made to prevent oscillation of a differential receiver when its inputs are in a tri-state mode is to provide an offset voltage, typically with a resistor placed in series with one input of the differential receiver, such that when both inputs of the differential receiver are at a logic low, oscillation will not occur since both differential inputs are not at the same voltage due to the voltage drop across the resistor. However, this attempt provides minimal noise margin and distorts the symmetry of the complementary output signals of the differential receiver.
Another attempt prior art has made to prevent oscillation of a differential receiver when its inputs are in a tri-state mode is to provide a third transistor coupled across one of the differentially coupled transistors of the differential receiver such that the collector and emitter of the third transistor is coupled respectively to the collector and emitter of one of the differentially coupled transistors of the differential receiver. Further, the base of the third transistor is held at a constant predetermined voltage such that when both inputs to the differential receiver go to a logic low (tri-state mode), the third transistor becomes active and forces the outputs of the differential receiver to a known logic state and thereby preventing oscillation. However, this attempt provides a little noise margin since the constant voltage at the base of the third transistor reduces the variation allowed at the inputs of the differential receiver.
Hence, a need exists for a differential receiver circuit which can detect when its inputs are in a tri-state mode and force the outputs thereof to a known logic state thereby preventing oscillation of the differential receiver circuit and can also achieve maximum noise margin without sacrificing the common mode range.